View HD404448_4250506.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

To all our customers
Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp. Customer Support Dept. April 1, 2003
Cautions
Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
HD404449 Series
Rev. 6.0 Sept. 1998 Description
The HD404449 Series is a HMCS400-series microcomputer designed to increase program productivity with large-capacity memory. Each microcomputer has four timers, two serial interfaces, A/D converter, input capture circuit, 32-kHz oscillator for clock, and four low-power dissipation modes. The HD404449 Series includes three chips: the HD404448 with 8-kword ROM; the HD404449 with 16kword ROM; and HD4074449 with 16-kword PROM (ZTATTM version). The HD4074449 is a PROM version (ZTATTM microcomputer). A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTATTM version is 27256-compatible.) ZTATTM: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
* 8,192-word x 10-bit ROM (HD404448) 16,384-word x 10-bit ROM (HD404449 and HD4074449) * 1,152-digit x 4-bit RAM * 64 I/O pins, including 10 high-current pins (15 mA, max) * Four timer/counters * Eight-bit input capture circuit * Three timer outputs (including two PWM outputs) * Two event counter inputs (including one double-edge function) * Two clock-synchronous 8-bit serial interfaces * A/D converter (4-channel x 8-bit) * Built-in oscillators Main clock: 4-MHz ceramic oscillator or crystal (an external clock is also possible) Subclock: 32.768-kHz crystal * Eleven interrupt sources Four by external sources, including two double-edge function Seven by internal sources
HD404449 Series
* Subroutine stack up to 16 levels, including interrupts * Four low-power dissipation modes Subactive mode Standby mode Watch mode Stop mode * One external input for transition from stop mode to active mode * Instruction cycle time: 1 s (fOSC = 4 MHz) * Two operating modes MCU mode (HD404448, HD404449) MCU/PROM mode (HD4074449)
Ordering Information
Type Mask ROM Product Name HD404448 Model Name HD404448H HD404448TF HD404449 HD404449H HD404449TF ZTATTM HD4074449 HD4074449H HD4074449TF 16,384 16,384 ROM (Words) 8,192 Package 80-pin plastic QFP (FP-80A) 80-pin plastic QFP (TFP-80F) 80-pin plastic QFP (FP-80A) 80-pin plastic QFP (TFP-80F) 80-pin plastic QFP (FP-80A) 80-pin plastic QFP (TFP-80F)
2
HD404449 Series
Pin Arrangement
AN1 AN0 AVCC VCC RC3 RC2 RC1 RC0 RB3 RB2 RB1 RB0 RA3 RA2 RA1 RA0 R93 R92 R91 R90 AN2 AN3 AVSS TEST OSC1 OSC2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
FP-80A TFP-80F
R83 R82 R81 R80 R73 R72 R71 R70 R63 R62 R61 R60 R53/SO2 R52/SI2 R51/SCK2 R50 R43/SO1 R42/SI1 R41/SCK1 R40/EVND
D10 D11 D12/STOPC D13/INT0 R00/INT1 R01/INT2 R02/INT3 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30/TOB R31/TOC R32/TOD R33/EVNB (Top view)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
HD404449 Series
Pin Description
Item Power supply Symbol VCC GND Test Reset Oscillator TEST RESET OSC 1 Pin Number I/O 77 10 4 7 5 I I I Function Applies power voltage Connected to ground Used for factory testing only: Connect this pin to V CC Resets the MCU Input/output pins for the internal oscillator circuit: Connect them to a ceramic oscillator, crystal, or connect OSC 1 to an external oscillator circuit
OSC 2 X1
6 8
O I Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to V CC and leave the X2 pin open.
X2 Port D0-D 11
9 11-22
O I/O Input/output pins addressed by individual bits; pins D0-D 9 are high-current pins that can each supply up to 15 mA I Input pins addressable by individual bits
D12, D13 R0 0-RC3 Interrupt INT0, INT1, INT2, INT3 Stop clear Serial interface STOPC SCK 1, SCK 2 SI 1, SI 2 SO1, SO2 Timer EVNB, EVND A/D converter AVCC
23, 24 25-76 24-27
I/O Input/output pins addressable in 4-bit units I Input pins for external interrupts
23 42, 46 43, 47 44, 48
I
Input pin for transition from stop mode to active mode
I/O Serial clock input/output pin I O O I Serial receive data input pin Serial transmit data output pin Timer output pins Event count input pins Power pin for A/D converter: Connect it to the same potential as V CC, as physically close to the VCC pin as possible Ground for AV CC: Connect it to the same potential as GND, as physically close to the GND pin as possible I Analog input pins for A/D converter
TOB, TOC, TOD 37-39 40, 41 78
AVSS AN 0-AN 3
3 79, 80, 1, 2
4
HD404449 Series
Block Diagram
RESET TEST STOPC OSC1 OSC2 X1 X2 VCC GND
System control
INT 0 INT 1 INT 2 INT 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D 10 D 11 D 12 D 13 R0 0 R0 1 R0 2 R0 3 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 R3 0 R3 1 R3 2 R3 3 R4 0 R4 1 R4 2 R4 3 R5 0 R5 1 R5 2 R5 3 R6 0 R6 1 R6 2 R6 3 R7 0 R7 1 R7 2 R7 3 R8 0 R8 1 R8 2 R8 3 R9 0 R9 1 R9 2 R9 3 RA0 RA1 RA2 RA3 RB 0 RB 1 RB 2 RB 3 RC 0 RC 1 RC 2 RC 3
External interrupt
RAM (1,152 x 4 bits) D port
High current pins
Timer A
W (2 bits) X (4 bits)
EVNB TOB
Timer B
TOC
Timer C
SPX (4 bits) Y (4 bits)
EVND TOD SI 1 SO 1 SCK 1 SI2 SO2 SCK2 AVCC AVSS AN0 AN1 AN2 AN3
Timer D Serial interface 1 Serial interface 2
Internal address bus
Internal data bus
SPY (4 bits)
ALU CPU ST CA (1 bit) (1 bit) A (4 bits) B (4 bits) SP (10 bits)
Instruction decoder
A/D converter
PC (14 bits)
ROM (16,384 x 10 bits) (8,192 x 10 bits)
RC port RB port RA port R9 port R8 port R7 port R6 port R5 port R4 port R3 port R2 port R1 port R0 port : Data bus
: Signal line
5
HD404449 Series
Memory Map
ROM Memory Map The ROM memory map is shown in figure 1 and described below.
0
Vector address 15 16 Zero-page subroutine (64 words) 63 64 Pattern (4,096 words) 4,095 4,096 HD404448 Program (8,192 words) 8,191 8,192 HD404449, HD4074449 Program (16,384 words) 16,383 $3FFF $1FFF $2000 $0FFF $1000 $003F $0040 $000F $0010 0 JMPL instruction 1 (Jump to RESET, STOPC routine) JMPL instruction 2 (Jump to INT0 routine) 3 JMPL instruction 4 (Jump to INT1 routine) 5 6 7 8 9 10 11 12 13 14 15 JMPL instruction (Jump to timer A routine) JMPL instruction (Jump to timer B, INT2 routine) JMPL instruction (Jump to timer C, INT3 routine) JMPL instruction (Jump to timer D, A/D routine) JMPL instruction (Jump to serial 1, serial 2 routine) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
$0000
Figure 1 ROM Memory Map Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$1FFF (HD404448), $0000-$3FFF (HD404449, HD4074449)): Used for program coding. RAM Memory Map The MCU contains a 1,152-digit x 4-bit RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM memory map is shown in figure 2 and described as follows.
6
HD404449 Series
0 RAM-mapped registers 64 80 Not used 144 $090 Memory registers (MR) $040 $050 $000 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 Interrupt control bits area (PMRA) Port mode register A Serial mode register 1A (SM1A) Serial data register 1 lower (SR1L) Serial data register 1 upper (SR1U) Timer mode register A (TMA) Timer mode register B1 (TMB1) (TRBL/TWBL) Timer B (TRBU/TWBU) (MIS) Miscellaneous register Timer mode register C1 (TMC1) (TRCL/TWCL) Timer C (TRCU/TWCU) Timer mode register D1 (TMD1) (TRDL/TWDL) Timer D (TRDU/TWDU) Timer mode register B2 (TMB2) Timer mode register C2 (TMC2) Timer mode register D2 (TMD2) A/D data register (AMR) A/D data register lower (ADRL) A/D data register upper (ADRU) Not used Serial mode register 2A Serial mode register 2B Serial data register 2 lower Serial data register 2 upper Not used (SM2A) W (SM2B) W (SR2L) R/W (SR2U) R/W W W R/W R/W W W R/W R/W W W R/W R/W W R/W R/W R/W R/W R/W W R R $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03F
*
Note
Data (464 digits x 2) V = 0 (bank 0) V = 1 (bank 1)
608 Data (144 digits) 752 960 Not used Stack (64 digits) 1023
$260 $2F0 $3C0 $3FF
$090 Data (464 digits) V=0 (bank = 0) Data (464 digits) V=1 (bank = 1) $25F
Register flag area Port mode register B Port mode register C (PMRB) (PMRC) W W W W W W
Detection edge select register 1 (ESR1) Detection edge select register 2 (ESR2)
Note: The data area has two banks: bank 0 (V = 0) to bank 1 (V = 1) R: Read only W: Write only R/W: Read/Write
Serial mode register 1B (SM1B) System clock select register (SSR) Not used Port D0 -D 3 DCR Port D4 -D 7 DCR Port D8 and D11 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Port R8 DCR Port R9 DCR Port RA DCR Port RB DCR Port RC DCR Not used V register
(DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) (DCR9) (DCRA) (DCRB) (DCRC)
W W W W W W W W W W W W W W W W R/W
* Two registers are mapped
on the same area. 10 11
Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00A Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00B
14 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E 15 Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F 17 Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011 18 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012
Figure 2 RAM Memory Map
7
HD404449 Series
RAM-Mapped Register Area ($000-$03F): * Interrupt Control Bits Area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. * Special Function Register Area ($004-$01F, $024-$03F) This area is used as mode registers and data registers for external interrupts, serial interface 1, serial interface 2, timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register Flag Area ($020-$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Data Area ($090-$2EF): 464 digits from $090 to $25F have two banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $260 to $2EF is accessed without setting the bank register. Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
8
HD404449 Series
Bit 3
0
Bit 2
Bit 1
Bit 0
IE (Interrupt enable flag)
$000
IM0 (IM of INT0)
IF0 (IF of INT0)
RSP (Reset SP bit)
1
IMTA (IM of timer A)
IMTC (IM of timer C)
IMS1 (IM of serial interface 1)
IFTA (IF of timer A) IFTC (IF of timer C) IFS1 (IF of serial interface 1)
IM1 (IM of INT1)
IMTB (IM of timer B) IMTD (IM of timer D)
IF1 (IF of INT1)
IFTB (IF of timer B) IFTD (IF of timer D)
$001
2
$002
3
$003
Interrupt control bits area
Bit 3
32
DTON (Direct transfer on flag)
Bit 2
ADSF (A/D start flag)
Bit 1
WDON (Watchdog on flag)
Bit 0
LSON (Low speed on flag) $020
33
RAME (RAM enable flag)
Not used
ICEF (Input capture error flag)
ICSF (Input capture status flag)
$021
34
IM3 (IM of INT3)
IMS2 (IM of serial interface 2)
IF3 (IF of INT3)
IFS2 (IF of serial interface 2)
IM2 (IM of INT2)
IMAD (IM of A/D)
IF2 (IF of INT2)
IFAD (IF of A/D)
$022
35
$023
IF: IM: IE: SP:
Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
9
HD404449 Series
SEM/SEMD IE IM LSON IF ICSF ICEF RAME RSP WDON ADSF DTON Not used Allowed REM/REMD Allowed TM/TMD Allowed
Not executed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed
Allowed Allowed Not executed Inhibited Allowed Not executed
Allowed Inhibited Inhibited Allowed Allowed Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
10
HD404449 Series
Bit 3 $000 $003 PMRA $004 SM1A $005 SR1L $006 SR1U $007 TMA $008 TMB1 $009 TRBL/TWBL $00A TRBU/TWBU $00B MIS $00C TMC1 $00D TRCL/TWCL $00E TRCU/TWCU $00F TMD1 $010 TRDL/TWDL $011 TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 AMR $016 ADRL $017 ADRU $018 SM2A $01B SM2B $01C SR2L $01D SR2U $01E $020 Register flag area $023 PMRB $024 PMRC $025 ESR1 $026 ESR2 $027 SM1B $028 SSR $029 DCD0 $02C DCD1 $02D DCD2 $02E DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 DCR4 $034 DCR5 $035 DCR6 $036 DCR7 $037 DCR8 $038 DCR9 $039 DCRA $03A DCRB $03B DCRC $03C V $03F Not used D13/INT0 R02/INT3 D12/STOPC R01/INT2 R40/EVND Not used *8 *12 Not used Port D3 DCR Port D7 DCR Port D11 DCR Port R03 DCR Port R13 DCR Port R23 DCR Port R33 DCR Port R43 DCR Port R53 DCR Port R63 DCR Port R73 DCR Port R83 DCR Port R93 DCR Port RA3 DCR Port RB3 DCR Port RC3 DCR Not used Port D2 DCR Port D6 DCR Port D10 DCR Port R02 DCR Port R12 DCR Port R22 DCR Port R32 DCR Port R42 DCR Port R52 DCR Port R62 DCR Port R72 DCR Port R82 DCR Port R92 DCR Port RA2 DCR Port RB2 DCR Port D1 DCR Port D5 DCR Port D9 DCR Port R01 DCR Port R11 DCR Port R21 DCR Port R31 DCR Port R41 DCR Port R51 DCR Port R61 DCR Port R71 DCR Port R81 DCR Port R91 DCR Port RA1 DCR Port RB1 DCR Port D0 DCR Port D4 DCR Port D8 DCR Port R00 DCR Port R10 DCR Port R20 DCR Port R30 DCR Port R40 DCR Port R50 DCR Port R60 DCR Port R70 DCR Port R80 DCR Port R90 DCR Port RA0 DCR Port RB0 DCR Port RC0 DCR *13 Notes: 1. Timer-A/time-base 2. Auto-reload on/off 3. Pull-up MOS control 4. Input capture selection 5. A/D conversion time 6. SO2 ouput control in idle states 7. Serial clock source selection 2 8. SO1 output level control in idle states 9. Serial clock source selection 1 10. 32-kHz oscillation stop 11. 32-kHz oscillation division ratio 12. System clock selection 13. Bank 0, 1 selection *9 Not used R00/INT1 R33/EVNB R51/SCK2 Not used Not used Not used *4 Analog channel selection *2 *3 *2 *1 *2 R52/SI2 R41/SCK1 Bit 2 Bit 1 Bit 0 Interrupt control bits area R53/SO2 R42/SI1 R43/SO1
Serial transmit clock speed selection 1 Serial data register 1 (lower digit) Serial data register 1 (upper digit) Clock source selection (timer A) Clock source selection (timer B) Timer B register (lower digit) Timer B register (upper digit) R43/SO1 PMOS control Interrupt frame period selection Clock source selection (timer C) Timer C register (lower digit) Timer C register (upper digit) Clock source selection (timer D) Timer D register (lower digit) Timer D register (upper digit) Not used Timer-B output mode selection Timer-C output mode selection Timer-D output mode selection Not used *5 A/D data register (lower digit) A/D data register (upper digit) Not used Serial transmit clock speed selection 2 R53/SO2 PMOS control *6 *7 Serial data register 2 (lower digit) Serial data register 2 (upper digit) Not used
INT3 detection edge selection EVND detection edge selection Not used *10 Not used *11
INT2 detection edge selection
Not used
Port RC2 DCR Port RC1 DCR Not used Not used Not used
Figure 5 Special Function Register Area
11
HD404449 Series
Memory registers MR(0) $040 64 MR(1) $041 65 MR(2) $042 66 MR(3) $043 67 MR(4) $044 68 MR(5) $045 69 MR(6) $046 70 MR(7) $047 71 MR(8) $048 72 MR(9) $049 73 MR(10) $04A 74 MR(11) $04B 75 MR(12) $04C 76 MR(13) $04D 77 MR(14) $04E 78 MR(15) $04F 79 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0
Bit 3 1020 1021 1022 $3FF 1023 ST PC 10 CA PC 3
Bit 2 PC13 PC9 PC6 PC2
Bit 1 PC 12 PC 8 PC 5 PC 1
Bit 0 PC11 PC7 PC4 PC0 $3FC $3FD $3FE $3FF
PC13 -PC0 : Program counter ST: Status flag CA: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
Bank register (V: $03F) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 -- -- 0 0 R/W V0
Not used Not used Not used
V0 0 1
Bank area selection Bank 0 is selected Bank 1 is selected
Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected.
Figure 7 Bank Register (V)
12
HD404449 Series
Functional Description
Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below.
3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: 1, no R/W 13 (PC) 9 1 1 1 1 5 (SP) 0 (ST) 0 (SPX) 0 (Y) 0 (X) 0 0 (W) 0 (A) 0 0
Figure 8 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing.
13
HD404449 Series
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1.
14
HD404449 Series
Table 1
Item Program counter Status flag Stack pointer Interrupt Interrupt enable flag flags/mask Interrupt request flag Interrupt mask I/O Port data register Data control register
Initial Values After MCU Reset
Abbr. (PC) (ST) (SP) (IE) (IF) (IM) (PDR) (DCD0- DCD2) (DCR0- DCRC) Port mode register A Port mode register B Port mode register C Detection edge select register 1 Detection edge select register 2 (PMRA) (PMRB) (PMRC) (ESR1) (ESR2) (TMA) Initial Value $0000 1 $3FF 0 0 1 Contents Indicates program execution point from start address of ROM area Enables conditional branching Stack level 0 Inhibits all interrupts Indicates there is no interrupt request Prevents (masks) interrupt requests
All bits 1 Enables output at level 1 All bits 0 Turns output buffer off (to high impedance) All bits 0 0000 - 000 0000 0000 00 - 0000 Refer to description of port mode register A Refer to description of port mode register B Refer to description of port mode register C Disables edge detection Disables edge detection Refer to description of timer mode register A
Timer/ counters, serial interface
Timer mode register A
Timer mode register B1 Timer mode register B2 Timer mode register C1 Timer mode register C2 Timer mode register D1 Timer mode register D2 Serial mode register 1A Serial mode register 1B Serial mode register 2A Serial mode register 2B Prescaler S Prescaler W
(TMB1) (TMB2) (TMC1) (TMC2) (TMD1) (TMD2) (SM1A) (SM1B) (SM2A) (SM2B) (PSS) (PSW)
0000 - - 00 0000 - 000 0000 0000 0000 - - 00 0000 - 000 $000 $00
Refer to description of timer mode register B1 Refer to description of timer mode register B2 Refer to description of timer mode register C1 Refer to description of timer mode register C2 Refer to description of timer mode register D1 Refer to description of timer mode register D2 Refer to description of serial mode register 1A Refer to description of serial mode register 1B Refer to description of serial mode register 2A Refer to description of serial mode register 2B -- --
15
HD404449 Series
Item Timer/ counters, serial interface Timer counter A Abbr. (TCA) Initial Value $00 Contents --
Timer counter B Timer counter C Timer counter D Timer write register B Timer write register C Timer write register D Octal counter A/D A/D mode register
(TCB) (TCC) (TCD) (TWBU, TWBL) (TWCU, TWCL) (TWDU, TWDL)
$00 $00 $00 $X0 $X0 $X0 000
-- -- -- -- -- -- -- Refer to description of A/D mode register Refer to description of operating modes Refer to description of timer C Refer to description of A/D converter Refer to description of operating modes Refer to description of timer D Refer to description of timer D Refer to description of operating modes, and oscillator circuit Refer to description of operating modes, and oscillator circuit Refer to description of RAM memory map
(AMR) (LSON)
00 - 0 0
Bit register Low speed on flag Watchdog timer on flag A/D start flag Direct transfer on flag Input capture status flag Input capture error flag Others Miscellaneous register System clock select register bits 2-0 Bank register
(WDON) 0 (ADSF) (DTON) (ICSF) (ICEF) (MIS) (SSR2- SSR0) (V) 0 0 0 0 0000 00 ---0
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist.
16
HD404449 Series
Status After Status After Cancellation of Stop Cancellation of Stop Mode by STOPC Input Mode by MCU Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Status After all Other Types of Reset Pre-stop-mode values are not guaranteed; values must be initialized by program
Item Carry flag
Abbr. (CA)
Accumulator B register W register X/SPX register Y/SPY register
(A) (B) (W) (X/SPX) (Y/SPY)
Serial data register (SRL, SRU) A/D data register RAM RAM enable flag (RAME) (ADRL, ADRU) Pre-stop-mode values are retained 1 Pre-stop-mode values are retained 0 0 0 0
Port mode register (PMRC12) 1 bit 2 System clock (SSR3) select register bit 3
Interrupts The MCU has 11 interrupt sources: four external signals (INT0 , INT1, INT 2, INT 3), four timer/counters (timers A, B, C, and D), two serial interfaces (serial 1, serial 2), and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Some vector addresses are shared by two different interrupts. They are timer B and INT 2, timer C and INT 3, timer D and A/D converter, and serial interface 1 and serial interface 2. So the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in table 3.
17
HD404449 Series
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities
Priority -- 1 2 3 4 5 6 7 Vector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E
Reset/Interrupt RESET, STOPC* INT0 INT1 Timer A Timer B, INT2 Timer C, INT3 Timer D, A/D Serial 1, Serial 2
Note: * The STOPC interrupt request is valid only in stop mode
18
HD404449 Series
$ 000,0 IE $ 000,2 IF0 $ 000,3 IM0 Priority control logic INT1 interrupt $ 001,0 IF1 $ 001,1 IM1 $ 001,2 IFTA $ 001,3 IMTA Timer B interrupt $ 002,0 IFTB $ 002,1 IMTB Timer C interrupt $ 002,2 IFTC $ 002,3 IMTC Timer D interrupt $ 003,0 IFTD $ 003,1 IMTD $ 003,2 Serial 1 interrupt IFS1 $ 003,3 IMS1 Note: $m,n is RAM address $m, bit number n. $ 022,0 IF2 INT2 interrupt $ 022,1 IM2 $ 022,2 IF3 INT3 interrupt $ 022,3 IM3 $ 023,0 IF A/D interrupt A/D $ 023,1 IM A/D $ 023,2 Serial 2 interrupt IFS2 $ 023,3 IMS2 Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address
INT0 interrupt
Vector address
Timer A interrupt
Figure 9 Interrupt Control Circuit
19
HD404449 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source Interrupt Control Bit IE IF0 IM0 IF1 IM1 IFTA IMTA IFTB IMTB + IF2 IM2 IFTC . IMTC + IF3 IM3 IFTD . IMTD + IFAD IMAD IFS1 . IMS1 + IFS2 IMS2 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
. . . . . . . .
INT0 1 1 * * *
INT1 1 0 1 * *
Timer A 1 0 0 1 *
Timer B or Timer C or Timer D or Serial 1 or INT3 A/D Serial 2 INT2 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0
*
*
*
*
1
0
0
*
*
*
*
*
1
0
*
*
*
*
*
*
1
Instruction cycles 1 2 3 4 5 6
Instruction execution*
Interrupt acceptance
Stacking IE reset Vector address generation
Execution of JMPL instruction at vector address
Note: *The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction.
Execution of instruction at start address of interrupt routine
Figure 10 Interrupt Processing Sequence
20
HD404449 Series
Power on
RESET = 1? Yes
No
Interrupt request? No
Yes
No
IE = 1? Yes
Reset MCU
Execute instruction
Accept interrupt
PC (PC) + 1
IE 0 Stack (PC) Stack (CA) Stack (ST)
PC $0002
Yes
INT0 interrupt? No
PC $0004
Yes
INT1 interrupt? No
PC $0006
Yes
Timer-A interrupt? No
PC $0008
Yes
Timer-B/INT2 interrupt? No
PC $000A
Yes
Timer-C/INT3 interrupt? No
PC $000C
Yes
Timer-D/A-D interrupt? No
PC $000E
(Serial 1, serial 2 interrupt)
Figure 11 Interrupt Processing Flowchart
21
HD404449 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4
IE 0 1
Interrupt Enable Flag (IE: $000, Bit 0)
Interrupt Enabled/Disabled Disabled Enabled
External Interrupts (INT0, INT1, INT2, INT3): Four external interrupt signals. External Interrupt Request Flags (IF0, IF1, IF2, IF3: $000, $001, $022): IF0 and IF1 are set at the falling edge of signals input to INT0 and INT1, and IF2 and IF3 are set at the rising or falling edge of signals input to INT2 and INT 3, as listed in table 5. The INT2 and INT 3 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Table 5
IF0-IF3 0 1
External Interrupt Request Flags (IF0-IF3: $000, $001, $022)
Interrupt Request No Yes
Detection edge selection register 1 (ESR1: $026) Bit Initial value Read/Write Bit name 3 0 W ESR13 2 0 W ESR12 1 0 W ESR11 0 0 W ESR10
ESR13 0
ESR12 0 1
INT3 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
ESR11 0
ESR10 0 1
INT2 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
1
0 1
1
0 1
Note: *Both falling and rising edges are detected.
Figure 12 Detection Edge Selection Register 1 (ESR1)
22
HD404449 Series
Detection edge selection register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W 1 -- -- 0 -- --
ESR22 Not used Not used
ESR23 0
ESR22 0 1
EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
1
0 1
Note: *Both falling and rising edges are detected.
Figure 13 Detection Edge Selection Register 2 (ESR2) External Interrupt Masks (IM0, IM1, IM2, IM3: $000, $001, $022): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6
IM0-IM3 0 1
External Interrupt Masks (IM0-1M3: $000, $001, $022)
Interrupt Request Enabled Disabled (Masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7
IFTA 0 1
Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
Interrupt Request No Yes
23
HD404449 Series
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8
IMTA 0 1
Timer A Interrupt Mask (IMTA: $001, Bit 3)
Interrupt Request Enabled Disabled (Masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 9. Table 9
IFTB 0 1
Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
Interrupt Request No Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 10. Table 10
IMTB 0 1
Timer B Interrupt Mask (IMTB: $002, Bit 1)
Interrupt Request Enabled Disabled (Masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 11. Table 11
IFTC 0 1
Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
Interrupt Request No Yes
24
HD404449 Series
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12. Table 12
IMTC 0 1
Timer C Interrupt Mask (IMTC: $002, Bit 3)
Interrupt Request Enabled Disabled (Masked)
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used, as listed in table 13. Table 13
IFTD 0 1
Timer D Interrupt Request Flag (IFTD: $003, Bit 0)
Interrupt Request No Yes
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 14. Table 14
IMTD 0 1
Timer D Interrupt Mask (IMTD: $003, Bit 1)
Interrupt Request Enabled Disabled (Masked)
Serial Interrupt Request Flags (IFS1: $003, Bit 2; IFS2: $023, Bit 2) Set when data transfer is completed or when data transfer is suspended, as listed in table 15. Table 15
IFS1, IFS2 0 1
Serial Interrupt Request Flag (IFS1: $003, Bit 2; IFS2: $023, Bit 2)
Interrupt Request No Yes
25
HD404449 Series
Serial Interrupt Masks (IMS1: $003, Bit 3; IMS2: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. Table 16
IMS1, IMS2 0 1
Serial Interrupt Mask (IMS1: $003, Bit 3; IMS2: $023, Bit 3)
Interrupt Request Enabled Disabled (Masked)
A/D Interrupt Request Flag (IFAD: $023, Bit 0): Set at the completion of A/D conversion, as listed in table 17. Table 17
IFAD 0 1
A/D Interrupt Request Flag (IFAD: $023, Bit 0)
Interrupt Request No Yes
A/D Interrupt Mask (IMAD: $023, Bit 1): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as listed in table 18. Table 18
IMAD 0 1
A/D Interrupt Mask (IMAD: $023, Bit 1)
Interrupt Request Enabled Disabled (Masked)
26
HD404449 Series
Operating Modes
The MCU has five operating modes as shown in table 19. The operations in each mode are listed in tables 20 and 21. Transitions between operating modes are shown in figure 14. Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1 and OSC2. Table 19 Operating Modes and Clock Status
Mode Name Active Standby Stop Watch Subactive*2 INT0 or timer A interrupt request from watch mode
SBY instruction STOP STOP Activation method RESET instruction when instruction when cancellation, TMA3 = 0 TMA3 = 1 interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) Status System oscillator OP OP OP Stopped OP*1 Stopped OP
Stopped OP
Subsystem OP oscillator Cancellation method RESET input, STOP/SBY instruction
RESET input, RESET input, RESET input, RESET input, interrupt request STOPC input in INT0 or timer A STOP/SBY stop mode interrupt request instruction
Note: OP implies in operation 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029). 2. Subactive mode is an optional function; specify it on the function option list.
27
HD404449 Series
Table 20
Function CPU RAM Timer A Timer B Timer C Timer D Serial 1, 2 A/D I/O
Operations in Low-Power Dissipation Modes
Stop Mode Reset Retained Reset Reset Reset Reset Reset Reset Reset*
1
Watch Mode Retained Retained OP Stopped Stopped Stopped Stopped* Stopped Retained
3
Standby Mode Retained Retained OP OP OP OP OP OP Retained
Subactive Mode*2 OP OP OP OP OP OP OP Stopped OP
Note: OP implies in operation 1. Output pins are at high impedance. 2. Subactive mode is an optional function specified on the function option list. 3. Transmission/reception is activated if a clock is input in external clock mode. However, all interrupts stop.
Table 21
I/O Status in Low-Power Dissipation Modes
Output Standby mode, watch mode Stop mode High impedance -- High impedance Input Active mode, subactive mode Input enabled Input enabled Input enabled
D0-D 11 D12-D 13 R0-RC
Retained -- Retained or output of peripheral functions
28
HD404449 Series
Reset by RESET input or by watchdog timer
Stop mode
(TMA3 = 0, SSR3 = 0)
RAME = 0 RESET1
RAME = 1 RESET2
STOPC
STOPC
Active mode STOP fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate Stop fcyc fcyc SBY Interrupt fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fcyc fcyc
(TMA3 = 0)
fOSC: fX: o CPU: o CLK: o PER:
Stop Oscillate Stop Stop Stop
Standby mode
(TMA3 = 0, SSR3 = 1)
STOP
fOSC: fX: o CPU: o CLK: o PER:
Stop Stop Stop Stop Stop
Watch mode
(TMA3 = 1) (TMA3 = 1, LSON = 0)
fOSC: fX: o CPU: o CLK: o PER:
Oscillate Oscillate Stop fW fcyc
SBY Interrupt
fOSC: fX: o CPU: o CLK: o PER:
Oscillate Oscillate fcyc fW fcyc
STOP INT0, timer A*1
fOSC: fX: o CPU: o CLK: o PER:
Stop Oscillate Stop fW Stop
*3
Main oscillation frequency Suboscillation frequency for time-base fOSC/4 fcyc: fSUB: fX/8 or fX/4 (software selectable) fW: fX/8 o CPU: System clock o CLK: Clock for time-base o PER: Clock for other peripheral functions LSON: Low speed on flag DTON: Direct transfer on flag
fOSC: fX:
Subactive mode fOSC: fX: o CPU: o CLK: o PER:
*2
STOP Stop Oscillate fSUB fW fSUB
*4
(TMA3 = 1, LSON = 1)
INT0, timer A*1
fOSC: fX: o CPU: o CLK: o PER:
Stop Oscillate Stop fW Stop
Notes: 1. 2. 3. 4.
Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) STOP/SBY (DTON = Don't care, LSON = 1)
Figure 14 MCU Status Transitions
29
HD404449 Series
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 15.
Stop Oscillator: Stop Suboscillator: Active/Stop Peripheral clocks: Stop All other clocks: Stop Standby Watch
Oscillator: Active Peripheral clocks: Active All other clocks: Stop
Oscillator: Stop Suboscillator: Active Peripheral clocks: Stop All other clocks: Stop
No
RESET = 1?
RESET = 1?
No
Yes No
STOPC = 0?
Yes
IF0 * IM0 = 1?
No
Yes Yes
IF1 * IM1 = 1?
No
Yes
IFTA * IMTA = 1?
No
IFTB * IMTB + IF2 * IM2 = 1?
Yes
No
IFTC * IMTC + IF3 * IM3 = 1?
RAME = 1
RAME = 0
Yes
No
IFTD * IMTD + IFAD * IMAD = 1?
Yes
No
IFS1* IMS1 + IFS2 * IMS2 = 1?
Yes (SBY only) (SBY only) (SBY only) (SBY only)
No
(SBY only)
Yes
Restart processor clocks
Restart processor clocks Execute next instruction
No
IF = 1, IM = 0, and IE = 1?
Yes
Reset MCU
Execute next instruction
Accept interrupt
Figure 15 MCU Operation Flowchart
30
,
HD404449 Series
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. Operation of the X1 and X2 oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029; operating: SSR3 = 0, stop: SSR3 = 1) (figure 26). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 41). Stop mode is terminated by a RESET input or a STOPC input as shown in figure 16. RESET or STOPC must be applied for at least one t RC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.
Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution tres tRC (stabilization period)
Figure 16 Timing of Stop Mode Cancellation
Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operates but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode.
Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC) for an INT0 interrupt, as shown in figure 17. Operation during mode transition is the same as that at standby mode cancellation (figure 15).
31
HD404449 Series
Oscillation stabilization period Active mode Watch mode Active mode
Interrupt strobe INT0 Interrupt request generation
(During the transition from watch mode to active mode only) Interrupt frame length T: t RC : Oscillation stabilization period
T
T Tx
t RC
Figure 17 Interrupt Frame Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions other than A/D conversion operate. However, because the operating clock is slow, the power dissipation becomes low, next to watch mode. The CPU instruction execution speed can be selected as 244 s or 122 s by setting bit 2 (SSR2) of the system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, oCLK is applied to timer A and the INT0 circuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, the timer-A/INT0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing.
32
HD404449 Series
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3
MIS2
MIS1 0
MIS0 0
T*1
tRC*1
Oscillation circuit conditions External clock input
Buffer control. Refer to figure 38.
0.24414 ms 0.12207 ms 0.24414 ms*2
0 1 1
1 0 1
15.625 ms 125 ms Not used
7.8125 ms 62.5 ms
Ceramic oscillator or crystal
--
Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used.
Figure 18 Miscellaneous Register (MIS) Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: * Set LSON to 0 and DTON to 1 in subactive mode. * Execute the STOP or SBY instruction. * The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (Figure 19). Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode: tRC < TD < T + tRC
33
HD404449 Series
STOP/SBY instruction execution Subactive mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T Interrupt frame length T: t RC : Oscillation stabilization period t RC MCU internal processing period Oscillation stabilization time
Active mode
Figure 19 Direct Transition Timing Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by a STOPC input as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode are used after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequences shown in figures 20 to 22. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.
34
HD404449 Series
Power on
RESET = 1 ? Yes RAME = 0
No
MCU operation cycle
Reset MCU
Figure 20 MCU Operating Sequence (Power On)
35
HD404449 Series
MCU operation cycle
IF = 1?
Yes
No
No
IM = 0 and IE = 1?
Instruction execution
Yes
Yes
SBY/STOP instruction?
IE 0 Stack (PC), (CA), (ST)
No
Low-power mode operation cycle
PC Next location
PC Vector address
IF: IM: IE: PC: CA: ST:
Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag
Figure 21 MCU Operating Sequence (MCU Operation Cycle)
36
HD404449 Series
Low-power mode operation cycle
IF = 1 and IM = 0?
No
Yes
Standby/Watch mode Stop mode
*
No
IF = 1 and IM = 0?
No
STOPC = 0?
Yes Hardware NOP execution Hardware NOP execution
Yes
RAME = 1
PC Next Iocation
PC Next Iocation
Reset MCU
Instruction execution
MCU operation cycle Note: * For IF and IM operation, refer to figure 15.
Figure 22 MCU Operating Sequence (Low-Power Mode Operation) Note: When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after the falling edge of INT 0 is shorter than the interrupt frame, INT 0 is not detected. Edge detection is shown in figure 23. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. In figure 24, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either.
37
HD404449 Series
When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than interrupt frame.
INT0
Sampling High Low Low
Figure 23 Edge Detection
INT0
INT0
Interrupt frame
A: Low
B: Low
Interrupt frame
A: High
B: High
(a) High level period
(b) Low level period
Figure 24 Sampling Example
38
HD404449 Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 25. As shown in table 22, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Bit 1 (SSR1) of the system clock select register (SSR: $029) must be selected according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 26). Note: If the system clock select register (SSR: $029) setting does not match the oscillator frequency, subsystems using the 32.768-kHz oscillation will malfunction.
LSON
OSC2 OSC1
1/4 System fOSC division oscillator circuit
fcyc tcyc
Timing generator circuit
oCPU System clock selection oPER
CPU with ROM, RAM, registers, flags, and I/O
Peripheral function interrupt
fX
X1 X2
Subsystem oscillator
fSUB 1/8 or 1/4 Timing division tsubcyc generator circuitNote circuit TMA3
1/8 division circuit
fW tWcyc
Timing generator circuit
Time-base clock oCLK selection
Time-base interrupt
Note: 1/8 or 1/4 division ratio can be selected by setting bit 2 of the system clock select register (SSR: $029).
Figure 25 Clock Generation Circuit
39
HD404449 Series
System clock select register (SSR: $029) Bit Initial value Read/Write Bit name 3 0 W SSR3 2 0 W SSR2 1 0 W SSR1 0 -- -- Not used
SSR2 0 1 SSR3 0 1
32-kHz oscillation division ratio selection fSUB = fX/8 fSUB = fX/4 32-kHz oscillation stop Oscillation operates in stop mode Oscillation stops in stop mode
SSR1 0 1
System clock selection 0.4 to 1.0 MHz 1.6 to 4.0 MHz
Figure 26 System Clock Select Register
D0 GND X2 X1 RESET OSC2 OSC1 TEST AVSS GND
Figure 27 Typical Layouts of Crystal and Ceramic Oscillator
40
HD404449 Series
Table 22 Oscillator Circuit Examples
Circuit Configuration External clock operation
External oscillator OSC 1
Circuit Constants
Open
OSC 2
Ceramic oscillator (OSC1, OSC 2)
C1 OSC1 Ceramic oscillator Rf OSC2 C2 GND
Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20%
Crystal oscillator (OSC1, OSC 2)
C1 OSC1 Crystal oscillator Rf OSC2 C2 GND L OSC1 C0 CS RS OSC2
Rf = 1 M 20% C1 = C2 = 10-22 pF 20% Crystal: Equivalent to circuit shown below C0 = 7 pF max RS = 100 max
Crystal oscillator (X1, X2)
C1 X1 Crystal oscillator X2 C2 GND L X1 C0 CS RS X2
Ceramic: 32.768 kHz: MX38T (Nippon Denpa Kogyo) C1 = C2 = 20 pF 20% RS: 14 k C0: 1.5 pF
Notes: 1. Since the circuit constants change depending on the crystal or ceramic resonator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC 2, X1, X2, and elements should be as short as possible, and must not cross other wiring (see figure 27). 3. If the 32.768-kHz crystal oscillator is not used, the X1 pin must be fixed to GND and X2 must be open.
41
HD404449 Series
Input/Output
The MCU has 64 input/output pins (D 0-D 11, R00-RC 3) and 2 input pins (D12, D13). The features are described below. * 10 pins (D0-D9) are high-current input/output pins. * The D12, D13, R00-R0 2, and R3 0-R5 3 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. * Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. * Peripheral function output pins are CMOS output pins. Only the R43/SO1 and R5 3/SO 2 pins can be set to NMOS open-drain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state. * Each input/output pin has a built-in pull-up MOS, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 28, programmable I/O circuits are listed in table 23, and I/O pin circuit types are shown in table 24. Table 23 Programmable I/O Circuits
0 0 0 PMOS NMOS Pull-up MOS Note: -- indicates off status. -- -- -- 1 -- -- -- 1 0 -- On -- 1 On -- -- 1 0 0 -- -- -- 1 -- -- On 1 0 -- On -- 1 On -- On
MIS3 (Bit 3 of MIS) DCD, DCR PDR CMOS buffer
42
HD404449 Series
HLT VCC Pull-up MOS VCC Pull-up control signal MIS3
Buffer control signal DCD, DCR
Output data
PDR
Input data Input control signal
Figure 28 I/O Buffer Configuration
43
HD404449 Series
Table 24
I/O Pin Type Input/output pins
Circuit Configurations of I/O Pins
Circuit
VCC HLT VCC Pull-up control signal Buffer control signal Output data Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal MIS3 DCR MIS2, SM2B2 PDR MIS3 DCD, DCR PDR
Pins D0-D 11 , R0 0-R0 3 R1 0-R1 3, R20-R2 3 R3 0-R3 3, R40-R4 2 R5 0-R5 2, R60-R6 3 R7 0-R7 3, R80-R8 3 R9 0-R9 3, RA0-RA 3 RB 0-RB 3, RC0-RC3 R4 3, R53
Output data Input data Input control signal
Input pins
Input data Input control signal
D12, D13
Peripheral Input/ output function pins pins
VCC
HLT VCC Pull-up control signal MIS3
SCK 1, SCK 2
Output data Input data
SCK 1 , SCK 2
SCK 1 , SCK 2 HLT
Output pins
VCC
VCC
Pull-up control signal
SO1, SO2
MIS3
PMOS control signal Output data
VCC
MIS2, SM2B2 SO 1 , SO 2
HLT VCC Pull-up control signal MIS3
TOB, TOC, TOD
Output data
TOB, TOC, TOD
44
HD404449 Series
I/O Pin Type Input pins Circuit
VCC HLT MIS3 PDR Input data Input data SI1, SI2,, INT1, etc INT0 , STOPC
Pins SI 1, SI 2, INT1, INT2, INT3, EVNB, EVND
INT0, STOPC
Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. 2. The HLT signal is 1 in watch and subactive modes.
D Port (D 0-D13): Consist of 12 input/output pins and 2 input pins addressed by one bit. D0-D11 are highcurrent I/O pins, and D12 and D13 are input-only pins. Pins D0-D 11 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D13 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0-DCD2: $02C-$02E) that are mapped to memory addresses (figure 29). Pins D 12 and D13 are multiplexed with peripheral function pins STOPC and INT0, respectively. The peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode register C (PMRC: $025) (figure 30). R Ports (R0 0-RC3): 52 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCRC: $030-$03C) that are mapped to memory addresses (figure 29). Pins R00-R02 are multiplexed with peripheral pins INT1-INT 3, respectively. The peripheral function modes of these pins are selected by bits 0-2 (PMRB0-PMRB2) of port mode register B (PMRB: $024) (figure 31). Pins R30-R32 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2 (TMB2: $013), bits 0-2 (TMC20-TMC22) of timer mode register C2 (TMC2: $014), and bits 0-3 (TMD20-TMD23) of timer mode register D2 (TMD2: $015) (figures 32, 33, and 34). Pins R33 and R40 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C (PMRC: $025) (figure 30). Pins R41-R43 are multiplexed with peripheral pins SCK 1, SI1, and SO1, respectively. The peripheral function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 35 and 36.
45
HD404449 Series
Ports R51-R5 3 are multiplexed with peripheral function pins SCK 2, SI2, SO2, respectively. The function modes of these pins can be selected by individual pins, by 2A setting bit 3 (SM2A3) of serial mode register 2A (SM2A: $01B), and bits 2 and 3 (PMRA2, PMRA3) of port mode register A (PMRA: $004) (figures 36 and 37). Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin other than input-only pins D 12 and D13 . The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 23 and figure 38). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k.
46
HD404449 Series
Data control register DCD0, DCD1 Bit Initial value Read/Write Bit name DCD2 Bit Initial value Read/Write Bit name DCR0 to DCRC Bit Initial value Read/Write Bit name (DCD0 to 2: $02C to $02E) (DCR0 to C: $030 to $03C) 2 0 W 1 0 W 0 0 W
3 0 W
DCD03, DCD02, DCD01, DCD00, DCD13 DCD12 DCD11 DCD10 3 0 W DCD23 2 0 W DCD22 1 0 W DCD21 0 0 W DCD20
3 0 W
2 0 W
1 0 W
0 0 W
DCR03- DCR02- DCR01- DCR00- DCRC3 DCRC2 DCRC1 DCRC0 CMOS Buffer On/Off Selection Off (high-impedance) On
All Bits 0 1
Correspondence between ports and DCD/DCR bits Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8 DCR9 DCRA DCRB DCRC Bit 3 D3 D7 D11 R03 R13 R23 R33 R43 R53 R63 R73 R83 R93 RA3 RB3 RC3 Bit 2 D2 D6 D10 R02 R12 R22 R32 R42 R52 R62 R72 R82 R92 RA2 RB2 RC2 Bit 1 D1 D5 D9 R01 R11 R21 R31 R41 R51 R61 R71 R81 R91 RA1 RB1 RC1 Bit 0 D0 D4 D8 R00 R10 R20 R30 R40 R50 R60 R70 R80 R90 RA0 RB0 RC0
Figure 29 Data Control Registers (DCD, DCR)
47
HD404449 Series
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 0 W PMRC3 2 0 W 1 0 W 0 0 W PMRC0
PMRC2* PMRC1
PMRC0 0 1 PMRC1 0 1 PMRC2 0 1 PMRC3 0 1
R33/EVNB mode selection R33 EVNB R40/EVND mode selection R40 EVND D12/STOPC mode selection D12 STOPC D13/INT0 mode selection D13 INT0
Note: *PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value.
Figure 30 Port Mode Register C (PMRC )
48
HD404449 Series
Port mode register B (PMRB: $024) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W 1 0 W 0 0 W
Not used PMRB2 PMRB1 PMRB0
PMRB0 0 1 PMRB1 0 1 PMRB2 0 1
R00/INT1 mode selection R00 INT1 R01/INT2 mode selection R01 INT2 R02/INT3 mode selection R02 INT3
Figure 31 Port Mode Register B (PMRB)
Timer mode register B2 (TMB2: $013) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 R/W 0 0 R/W TMB20
Not used Not used TMB21
TMB21 0
TMB20 0 1
R30/TOB mode selection R30 TOB TOB TOB R30 port Toggle output 0 output 1 output
1
0 1
Figure 32 Timer Mode Register B2 (TMB2)
49
HD404449 Series
Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- 2 0 R/W 1 0 R/W TMC21 0 0 R/W TMC20
Not used TMC22
TMC22 0
TMC21 0
TMC20 0 1
R31/TOC mode selection R31 TOC TOC TOC -- R31 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1
0 1 TOC PWM output
Figure 33 Timer Mode Register C2 (TMC2)
50
HD404449 Series
Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD23 0
TMD22 0
TMD21 0
TMD20 0 1
R32/TOD mode selection R32 TOD TOD TOD -- R32 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1
0 1 TOD R32 PWM output Input capture (R32 port)
1
Don't care Don't care Don't care
Figure 34 Timer Mode Register D2 (TMD2)
51
HD404449 Series
Serial mode register 1A (SM1A: $005) Bit Initial value Read/Write Bit name 3 0 W SM1A3 2 0 W SM1A2 1 0 W SM1A1 0 0 W SM1A0
SM1A3 0 1
R41/SCK1 mode selection R41 SCK1
SM1A2 0
SM1A1 0
SM1A0 0 1
SCK1 Output Output Output Output Output Output Output Input
Clock source Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock
Prescaler division ratio /2048 /512 /128 /32 /8 /2 -- --
1
0 1
1
0
0 1
1
0 1
Figure 35 Serial Mode Register 1A (SM1A)
52
HD404449 Series
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 0 W PMRA3 2 0 W 1 0 W 0 0 W
PMRA2 PMRA1 PMRA0
PMRA0 0 1 PMRA1 0 1 PMRA2 0 1 PMRA3 0 1
R43/SO1 mode selection R43 SO1 R42/SI1 mode selection R42 SI1 R53/SO2 mode selection R53 SO2 R52/SI2 mode selection R52 SI2
Figure 36 Port Mode Register A (PMRA)
53
HD404449 Series
Serial mode register 2A (SM2A: $01B) Bit Initial value Read/Write Bit name 3 0 W SM2A3 2 0 W SM2A2 1 0 W SM2A1 0 0 W SM2A0
SM2A3 0 1
R51/SCK2 mode selection R51 SCK2
SM2A2 0
SM2A1 0
SM2A0 0 1
SCK2 Output Output Output Output Output Output Output Input
Clock source Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock
Prescaler division ratio /2048 /512 /128 /32 /8 /2 -- --
1
0 1
1
0
0 1
1
0 1
Figure 37 Serial Mode Register 2A (SM2A)
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3 0 1
Pull-up MOS on/off selection Off On
MIS2 0 1
CMOS buffer on/off selection for pin R43/SO1 On Off
MIS1
MIS0
tRC selection. Refer to figure 18 in the operation modes section.
Figure 38 Miscellaneous Register (MIS)
54
HD404449 Series
Prescalers
The MCU has the following two prescalers, S and W. The prescaler operating conditions are listed in table 25, and the prescaler output supply is shown in figure 39. The timer A-D input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in stop, watch, and subactive modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. Table 25
Prescaler Prescaler S
Prescaler Operating Conditions
Input Clock System clock (in active and standby mode), Subsystem clock (in subactive mode) 32-kHz crystal oscillation Reset Conditions MCU reset Stop Conditions MCU reset, stop mode, watch mode
Prescaler W
Software
MCU reset, stop mode
Subsystem clock
fX /8
Prescaler W
Timer A Timer B Timer C
fX /4 or fX /8
System clock
Clock selector
Prescaler S
Timer D Serial 1 Serial 2
Figure 39 Prescaler Output Supply
55
HD404449 Series
Timers
The MCU has four timer/counters (A to D). * * * * Timer A: Timer B: Timer C: Timer D: Free-running timer Multifunction timer Multifunction timer Multifunction timer
Timer A is an 8-bit free-running timer. Timers B-D are 8-bit multifunction timers, whose functions are listed in table 26. The operating modes are selected by software. Table 26
Functions Clock source Prescaler S Prescaler W External event Timer functions Free-running Time-base Event counter Reload Watchdog Input capture Timer outputs Toggle 0 output 1 output PWM Note: -- means not available.
Timer Functions
Timer A Available Available -- Available Available -- -- -- -- -- -- -- -- Timer B Available -- Available Available -- Available Available -- -- Available Available Available -- Timer C Available -- -- Available -- -- Available Available -- Available Available Available Available Timer D Available -- Available Available -- Available Available -- Available Available Available Available Available
56
HD404449 Series
Timer A Timer A Functions: Timer A has the following functions. * Free-running timer * Clock time-base The block diagram of timer A is shown in figure 40.
Timer A interrupt request flag (IFTA)
32.768-kHz oscillator
1/4
1/2 2 fW 1/2 twcyc
fW twcyc
Prescaler W (PSW)
/2 /8 / 16 / 32
Selector Internal data bus 57 Selector Clock Timer counter A (TCA) Overflow
Selector
/2 /4 /8 / 32 / 128 / 512 / 1024 / 2048
System clock
o PER
Prescaler S (PSS)
3 Timer mode register A (TMA)
Figure 40 Timer A Block Diagram Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. * Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software.
HD404449 Series
Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 41.
Timer mode register A (TMA: $008) Bit Initial value Read/Write Bit name 3 0 W TMA3 2 0 W TMA2 1 0 W TMA1 0 0 W TMA0
Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency Operating mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Don't care PSS PSS PSS PSS PSS PSS PSS PSS PSW PSW PSW PSW PSW Inhibited PSW and TCA reset 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc 32tWcyc 16tWcyc 8tWcyc 2tWcyc 1/2tWcyc Time-base mode Timer A mode
Notes: 1. tWcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur.
Figure 41 Timer Mode Register A (TMA)
58
HD404449 Series
Timer B Timer B Functions: Timer B has the following functions. * Free-running/reload timer * External event counter * Timer output operation (toggle, 0, and 1 outputs) The block diagram of timer B is shown in figure 42.
Timer B interrupt request flag (IFTB) TOB Timer output control logic
Timer read register BU (TRBU) Timer read register BL (TRBL) Clock Timer counter B (TCB) Overflow
Timer output control
Selector
/2 /4 /8 / 32 / 128 / 512
EVNB System clock o PER
/ 2048
Timer write register BU (TWBU) Timer write register BL (TWBL)
Prescaler S (PSS) Free-running/ Reload control 3
Timer mode register B1 (TMB1)
2 Timer mode register B2 (TMB2)
Figure 42 Timer B Block Diagram
Internal data bus 59
HD404449 Series
Timer B Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer B is used as an external event counter by selecting external event input as the input clock source. In this case, pin R33/EVNB must be set to EVNB by port mode register C (PMRC: $025). Timer B is incremented by one at each falling edge of signals input to pin EVNB. Other operations are basically the same as the free-running/ reload timer operation. * Timer output operation: The following three output modes can be selected for timer B by setting timer mode register B2 (TMB2: $013). Toggle 0 output 1 output By selecting the timer output mode, pin R30/TOB is set to TOB. The output from TOB is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer B has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. The output waveform is shown in figure 43. 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is low.
60
HD404449 Series
Toggle output waveform (timers B, C, and D) Free-running timer
256 clock cycles Reload timer
256 clock cycles
(256 - N) clock cycles (256 - N) clock cycles
PWM output waveform (timers C and D) T x (N + 1)
TMC13 = 0 TMD13 = 0 T x 256
T TMC13 = 1 TMD13 = 1
T x (256 - N) Note: The waveform is always fixed low when N = $FF. T: Input clock period to counter (figures 52 and 59) N: The value of the timer write register
Figure 43 Timer Output Waveform Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register C (PMRC: $025)
* Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 44. It is reset to $0 by MCU reset.
61
HD404449 Series
Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.
Timer mode register B1 (TMB1: $009) Bit Initial value Read/Write Bit name 3 0 W TMB13 2 0 W TMB12 1 0 W TMB11 0 0 W TMB10
TMB13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMB12 0
TMB11 0
TMB10 0 1
Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R33/EVNB (External event input)
1
0 1
1
0
0 1
1
0 1
Figure 44 Timer Mode Register B1 (TMB1) * Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output mode as shown in figure 45. It is reset to $0 by MCU reset.
62
HD404449 Series
Timer mode register B2 (TMB2: $013) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 R/W 0 0 R/W TMB20
Not used Not used TMB21
TMB21 0
TMB20 0 1
R30/TOB mode selection R30 TOB TOB TOB R30 port Toggle output 0 output 1 output
1
0 1
Figure 45 Timer Mode Register B2 (TMB2) * Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit (TWBL) and the upper digit (TWBU) as shown in figures 46 and 47. The lower digit is reset to $0 by MCU reset, but the upper digit value is invalid. Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B.
Timer write register B (lower digit) (TWBL: $00A) Bit Initial value Read/Write Bit name 3 0 W TWBL3 2 0 W TWBL2 1 0 W TWBL1 0 0 W TWBL0
Figure 46 Timer Write Register B Lower Digit (TWBL)
Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWBU3 W TWBU2 W TWBU1 W TWBU0
Figure 47 Timer Write Register B Upper Digit (TWBU)
63
HD404449 Series
* Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit (TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 48 and 49). The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU is read can be obtained.
Timer read register B (lower digit) (TRBL: $00A) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRBL3 R TRBL2 R TRBL1 R TRBL0
Figure 48 Timer Read Register B Lower Digit (TRBL)
Timer read register B (upper digit) (TRBU: $00B) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRBU3 R TRBU2 R TRBU1 R TRBU0
Figure 49 Timer Read Register B Upper Digit (TRBU) * Port mode register C (PMRC: $025): Write-only register that selects R33/EVNB pin function as shown in figure 50. It is reset to $0 by MCU reset.
64
HD404449 Series
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 0 W PMRC3 2 0 W 1 0 W 0 0 W
PMRC2 PMRC1 PMRC0
PMRC0 0 1 PMRC1 0 1 PMRC2 0 1 PMRC3 0 1
R33/EVNB mode selection R33 EVNB R40/EVND mode selection R40 EVND D12/STOPC mode selection D12 STOPC D13/INT0 mode selection D13 INT0
Figure 50 Port Mode Register C (PMRC) Timer C Timer C Functions: Timer C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 51.
65
HD404449 Series
System reset signal Watchdog on flag (WDON) Watchdog timer control logic Timer C interrupt request flag (IFTC)
TOC
Timer output control logic Timer read register CU (TRCU) Timer output control Timer read register CL (TRCL) Clock Timer counter C (TCC) Overflow
Selector /2 /4 /8 /32 /128 /512 /1024 /2048
Timer write register CU (TWCU) Free-running /Reload control 3 Timer mode register C1 (TMC1) Timer write register CL (TWCL)
System oPER clock
Prescaler S (PSS)
3 Timer mode register C2 (TMC2)
Figure 51 Timer C Block Diagram Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again.
66
Internal data bus
HD404449 Series
The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. * Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output
By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 43.
Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F)
* Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and prescaler division ratio as shown in figure 52. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. * Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode as shown in figure 53. It is reset to $0 by MCU reset.
67
HD404449 Series
* Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL) and an upper digit (TWCU) as shown in figures 54 and 55. The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit as shown in figures 56 and 57. The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B).
Timer mode register C1 (TMC1: $00D) Bit Initial value Read/Write Bit name 3 0 W TMC13 2 0 W TMC12 1 0 W TMC11 0 0 W TMC10
TMC13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMC12 0
TMC11 0
TMC10 0 1
Input clock period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc
1
0 1
1
0
0 1
1
0 1
Figure 52 Timer Mode Register C1 (TMC1)
68
HD404449 Series
Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- 2 0 R/W 1 0 R/W TMC21 0 0 R/W TMC20
Not used TMC22
TMC22 0
TMC21 0
TMC20 0 1
R31/TOC mode selection R31 TOC TOC TOC -- R31 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1
0 1 TOC PWM output
Figure 53 Timer Mode Register C2 (TMC2)
Timer write register C (lower digit) (TWCL: $00E) Bit Initial value Read/Write Bit name 3 0 W TWCL3 2 0 W TWCL2 1 0 W TWCL1 0 0 W TWCL0
Figure 54 Timer Write Register C Lower Digit (TWCL)
Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWCU3 W TWCU2 W TWCU1 W TWCU0
Figure 55 Timer Write Register C Upper Digit (TWCU)
69
HD404449 Series
Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCL3 R TRCL2 R TRCL1 R TRCL0
Figure 56 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCU3 R TRCU2 R TRCU1 R TRCU0
Figure 57 Timer Read Register C Upper Digit (TRCU) Timer D Timer D Functions: Timer D has the following functions. * * * * Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer
The block diagram for each operation mode of timer D is shown in figures 58 (A) and (B).
70
HD404449 Series
Timer D interrupt request flag (IFTD) TOD Timer output control logic
Timer read register DU (TRDU)
Timer output control Timer read register DL (TRDL) Clock Timer counter D (TCD) Overflow
Selector EVND Edge detection logic oPER
/2048
/2 /4 /8 /32 /128 /512
Free-running/ Reload control 3
Timer write register DL (TWDL)
System clock
Prescaler S (PSS)
Timer mode register D1 (TMD1) 3 Timer mode register D2 (TMD2) Edge detection control
2 Edge detection selection register 2 (ESR2)
Figure 58 (A) Timer D Block Diagram (Free-Running/Reload Timer)
Internal data bus 71
Timer write register DU (TWDU)
HD404449 Series
Input capture status flag (ICSF) Input capture error flag (ICEF) Error control logic Timer D interrupt request flag (IFTD)
Timer read register DU (TRDU) Timer read register DL (TRDL) EVND Edge detection logic Read signal Clock Input capture timer control Internal data bus Timer counter D (TCD) Overflow
Selector
3 Timer mode register D1 (TMD1)
System clock
oPER Prescaler S (PSS) Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2)
Figure 58 (B) Timer D Block Diagram (Input Capture Timer)
72
/2048
/2 /4 /8 /32 /128 /512
HD404449 Series
Timer D Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. * Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output
By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: The operation is basically the same as that of timer-C's PWM output.
* Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027).
73
HD404449 Series
When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00. Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027)
* Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the freerunning/reload timer function, input clock source, and the prescaler division ratio as shown in figure 59. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. * Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation as shown in figure 60. It is reset to $0 by MCU reset.
74
HD404449 Series
Timer mode register D1 (TMD1: $010) Bit Initial value Read/Write Bit name 3 0 W TMD13 2 0 W TMD12 1 0 W TMD11 0 0 W TMD10
TMD13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMD12 0
TMD11 0
TMD10 0 1
Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R40/EVND (External event input)
1
0 1
1
0
0 1
1
0 1
Figure 59 Timer Mode Register D1 (TMD1) * Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit (TWDL) and an upper digit (TWDU) as shown in figures 61 and 62. The operation of timer write register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). * Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit (TRDL) and an upper digit (TRDU) as shown in figures 63 and 64. The operation of timer read register D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. * Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown in figure 50. It is reset to $0 by MCU reset. * Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 65. It is reset to $0 by MCU reset.
75
HD404449 Series
Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD23 0
TMD22 0
TMD21 0
TMD20 0 1
R32/TOD mode selection R32 TOD TOD TOD -- R32 port Toggle output 0 output 1 output Inhibited
1
0 1
1
0
0 1
1
0 1 TOD R32 PWM output Input capture (R32 port)
1
Don't care Don't care Don't care
Figure 60 Timer Mode Register D2 (TMD2)
Timer write register D (lower digit) (TWDL: $011) Bit Initial value Read/Write Bit name 3 0 W TWDL3 2 0 W TWDL2 1 0 W TWDL1 0 0 W TWDL0
Figure 61 Timer Write Register D Lower Digit (TWDL)
Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWDU3 W TWDU2 W TWDU1 W TWDU0
Figure 62 Timer Write Register D Upper Digit (TWDU)
76
HD404449 Series
Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDL3 R TRDL2 R TRDL1 R TRDL0
Figure 63 Timer Read Register D Lower Digit (TRDL)
Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDU3 R TRDU2 R TRDU1 R TRDU0
Figure 64 Timer Read Register D Upper Digit (TRDU)
Detection edge register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W 1 -- -- 0 -- --
ESR22 Not used Not used
ESR23 0
ESR22 0 1
EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
1
0 1
Note: * Both falling and rising edges are detected.
Figure 65 Detection Edge Select Register 2 (ESR2) Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 27. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle.
77
HD404449 Series
Table 27 PWM Output Following Update of Timer Write Register
PWM Output Mode Free running Timer Write Register is Updated during High PWM Output
Timer write register updated to value N
Timer Write Register is Updated during Low PWM Output
Timer write register updated to value N
Interrupt request
Interrupt request
T x (255 - N) T x (N + 1)
T x (N' + 1) T x (255 - N) T x (N + 1)
Reload
Timer write register updated to value N
Interrupt request
Timer write register updated to value N
Interrupt request
T
T x (255 - N)
T
T T x (255 - N) T
78
HD404449 Series
Serial Interface
The MCU has two channels of serial interface. The transfer and receive start instructions differ according to the serial interface channel, but other functions are the same. The serial interface serially transfers or receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for serial interfaces 1 and 2 as follows. Serial interface 1 * * * * * * * Serial data register 1 (SR1L: $006, SR1U: $007) Serial mode register 1A (SM1A: $005) Serial mode register 1B (SM1B: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector
Serial interface 2 * * * * * * Serial data register 2 (SR2L: $01D, SR2U: $01E) Serial mode register 2A (SM2A: $01B) Serial mode register 2B (SM2B: $01C) Port mode register A (PMRA: $004) Octal counter (OC) Selector
The block diagram of serial interfaces 1 and 2 are shown in figure 66.
79
HD404449 Series
Octal counter (OC1, OC2)
Serial interrupt request flag (IFS1, IFS2)
Idle control logic SO1 , SO2 I/O control logic SCK1 , SCK2 Clock Serial data register (SR1L/U, SR2L/U) Transfer control Internal data bus
SI1 , SI 2 Selector 1/2 1/2
Selector
3 Serial mode register 1A, 2A (SM1A, SM2A)
System clock
oPER
Prescaler S (PSS)
/2048
/8 /32 /128 /512
/2
Serial mode register 1B, 2B (SM1B, SM2B)
Figure 66 Serial Interfaces 1 and 2 Block Diagram Serial Interface Operation Selecting and Changing the Operating Mode: Tables 28 (A) and 28 (B) list the serial interfaces' operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004), serial mode register 1A (SM1A: $005), and serial mode register 2A (SM2A: $01B) settings; to change the operating mode of serial interface 1, always initialize the serial interface internally by writing data to serial mode register 1A; and to change the operating mode of serial interface 2, always initialize the serial interface internally by writing data to serial mode register 2A. Note that serial interface
80
HD404449 Series
1 is initialized by writing data to serial mode register 1A, and serial interface 2 is initialized by writing data to serial mode register 2A. Refer to the following section Registers for Serial Interface for details. Pin Setting: The R41/SCK 1 pin is controlled by writing data to serial mode register 1A (SM1A: $005). The R5 1/SCK 2 pin is controlled by writing data to serial mode register 2A (SM2A: $01B). Pins R42/SI 1, R4 3/SO 1, R5 2/SI 2, and R5 3/SO 2 are controlled by writing data to port mode register A (PMRA: $004). Refer to the following section Registers for Serial Interface for details. Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). The transmit clock source of serial interface 2 is set by writing data to serial mode register 2A (SM2A: $01B) and serial mode register 2B (SM2B: $01C). Refer to the following section Registers for Serial Interface for details. Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L: $006, SR1U: $007). Transmit data of serial interface 2 is set by writing data to serial data register 2 (SR2L: $01D, SR2U: $01E). Receive data of serial interface 1 is obtained by reading the contents of serial data register 1. Receive data of serial interface 2 is obtained by reading the contents of serial data register 2. The serial data is shifted by each serial interface transmit clock and is input from or output to an external system. The output level of the SO1 and SO2 pins is invalid until the first data of each serial interface is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: Serial interface 1 is activated by the STS instruction. Serial interface 2 is activated by a dummy read of serial mode register 2A (SM2A: $01B), which will be referred to as SM2A read. The octal counter is reset to 000 by the STS instruction (serial interface 2 is SM2A read), and it increments at the rising edge of the transmit clock for each serial interface. When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) for serial interface 1 and serial 2 interrupt request flag (IFS2: $023, bit 2) for serial interface 2 are set, and the transfer stops. When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM1A0-SM1A2) of serial mode register 1A (SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 29. When the prescaler output is selected as the transmit clock of serial interface 2, the transmit clock frequency is selected as 4t cyc to 8192tcyc by setting bits 0 to 2 (SM2A0- SM2A2) of serial mode register 2A (SM2A: $01B) and bit 0 (SM2B0) of serial mode register 2B (SM2B: $01C). Note: To start serial interface 2, simply read serial mode register 2A by using the instruction that compares serial mode register 2A (SM2A: $01B) with the accumulator. Serial mode register 2A (SM2A: $01B) is a read-only register, so $0 can be read.
81
HD404449 Series
Table 28 (A)
SM1A Bit 3 1
Serial Interface 1 Operating Modes
PMRA Bit 1 0 Bit 0 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
Table 28 (B)
SM2A Bit 3 1
Serial Interface 2 Operating Modes
PMRA Bit 3 0 Bit 2 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
Table 29
SM1B/ SM2B Bit 0 0
Serial Transmit Clock (Prescaler Output)
SM1A/ SM2A Bit 2 0 Bit 1 0 Bit 0 0 1 1 0 1 1 0 0 1 Prescaler Division Ratio / 2048 / 512 / 128 / 32 /8 /2 / 4096 / 1024 / 256 / 64 / 16 /4 Transmit Clock Frequency 4096t cyc 1024t cyc 256t cyc 64t cyc 16t cyc 4t cyc 8192t cyc 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc
1
0
0
0 1
1
0 1
1
0
0 1
82
HD404449 Series
Operating States: The serial interface has the following operating states; transitions between them are shown in figure 67. STS wait state (serial interface 2 is in SM2A read wait state) Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode)
The operation state of serial interface 2 is the same as serial interface 1 except that the STS instruction of serial interface 1 changes to SM2A read. The following shows the operation state of serial interface 1. * STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), serial interface 1 enters transmit clock wait state.
External clock mode
STS wait state (Octal counter = 000, transmit clock disabled)
00
MCU reset
SM1A write
04 01 STS instruction 02 Transmit clock
06 SM1A write (IFS 1)
Transmit clock wait state (Octal counter = 000)
Transfer state (Octal counter = 000)
03 8 transmit clocks
05 STS instruction (IFS 1)
Internal clock mode
STS wait state (Octal counter = 000, transmit clock disabled)
SM1A write 18 Continuous clock output state (PMRA 0, 1 = 00)
10
MCU reset
13 SM1A write 14 11 STS instruction
8 transmit clocks
16
SM1A write (IFS 1)
Transmit clock 17
12 Transmit clock Transmit clock wait state (Octal counter = 000) 15 STS instruction (IFS 1) Transfer state (Octal counter = 000)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 67 Serial Interface State Transitions * Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the
83
HD404449 Series
serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04, 14) in transmit clock wait state. * Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial interface 1, and STS wait state is entered. If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK 1 pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait state is entered. Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state and when serial interface 2 is in SM2A read wait state and transmit clock state, the output of each serial output pin, SO1 and SO2, can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1, or bit 1 (SM2B1) of serial mode register 2B (SM2B: $01C) to 0 or 1. The output level control example of serial interface 1 is shown in figure 68. Note that the output level cannot be controlled in transfer state.
84
,
Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SM1A write SM1B write External clock selection Output level control in idle states Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin Undefined LSB IFS1 External clock mode Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SM1A write SM1B write Internal clock selection Output level control in idle states Data write for transmission SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin Undefined LSB IFS1 Internal clock mode
HD404449 Series
Transmit clock wait state STS wait state
Dummy write for state transition Output level control in idle states
MSB
Flag reset at transfer completion
STS wait state
Output level control in idle states
MSB
Flag reset at transfer completion
Figure 68 Example of Serial Interface 1 Operation Sequence
85
HD404449 Series
Transmit Clock Error Detection (In External Clock Mode): Each serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 69. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer is completed and IFS1 is reset, writing to serial mode register 1A (SM1A: $005) changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the serial 1 interrupt request flag (IFS1: $003, bit 2) is set again, and therefore the error can be detected. The same applies to serial interface 2. Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1A (SM1A: $005) and serial mode register 2A (SM2A: $01B) again. * Serial 1 interrupt request flag (IFS1: $003, bit 2) and serial 2 interrupt request flag (IFS2: $023, bit 2) set: For serial interface 1, if the state is changed from transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag (IFS1: $003, bit 2) is not set. In the same way for serial interface 2, if the state is changed from transfer state to another by writing to serial mode register 2A (SM2A: $01B) or by executing the STS instruction during the first low pulse of the transmit clock, the serial 2 interrupt request flag (IFS2: $023, bit 2) is not set. To set the serial 1 interrupt request flag (IFS1: $003, bit 2), a serial mode register 1A (SM1A: $005) write or STS instruction execution must be programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing the input instruction to port R4. To set the serial 2 interrupt request flag (IFS2: $023, bit 2), a serial mode register 2A (SM2A: $01B) write or SM2A instruction execution must be programmed to be executed after confirming that the SCK 2 pin is at 1, that is, after executing the input instruction to port R5.
86

Transmit clock wait state State SCK 1 pin (input) 1 2 SM1A write IFS1
HD404449 Series
Transfer completion (IFS1 1)
Interrupts inhibited
IFS1 0
SM1A write
IFS1 = 1
Yes
Transmit clock error processing
No Normal termination
Transmit clock error detection flowchart
Transmit clock wait state Transfer state
Transfer state
Noise 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SM1A is written, IFS1 is set.
Flag set because octal counter reaches 000.
Flag reset at transfer completion.
Transmit clock error detection procedures
Figure 69 Transmit Clock Error Detection
87
HD404449 Series
Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. For serial interface 1 * Serial mode register 1A (SM1A: $005) * Serial mode register 1B (SM1B: $028) * Serial data register 1 (SR1L: $006, SR1U: $007) * Port mode register A (PMRA: $004) * Miscellaneous register (MIS: $00C) For serial interface 2 * Serial mode register 2A (SM2A: $01B) * Serial mode register 2B (SM2B: $01C) * Serial data register 2 (SR2L: $01D, SR2U: $01E) * Port mode register A (PMRA: $004) Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 70). * * * * R4 1/SCK 1 pin function selection Serial interface 1 transmit clock selection Serial interface 1 prescaler division ratio selection Serial interface 1 initialization
Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that.
88
HD404449 Series
Serial mode register 1A (SM1A: $005) Bit Initial value Read/Write Bit name 3 0 W SM1A3 2 0 W SM1A2 1 0 W SM1A1 0 0 W SM1A0
SM1A3 0 1
R41/SCK1 mode selection R41 SCK1
SM1A2 0
SM1A1 0
SM1A0 0 1
SCK1 Output
Clock source Prescaler
Prescaler division ratio Refer to table 29
1
0 1
1
0
0 1
1
0 1
Output Input
System clock External clock
-- --
Figure 70 Serial Mode Register 1A (SM1A) Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 71). * Serial interface 1 prescaler division ratio selection * Serial interface 1 output level control in idle states Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit 0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO1 pin is controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is written to.
89
HD404449 Series
Serial mode register 1B (SM1B: $028) Bit Initial value Read/Write Bit name 3 -- -- 2 -- --
1 Undefined W
0 0 W SM1B0
Not used Not used SM1B1
SM1B1 0 1
Output level control in idle states Low level High level
SM1B0 0 1
Transmit clock division ratio Prescaler output divided by 2 Prescaler output divided by 4
Figure 71 Serial Mode Register 1B (SM1B) Serial Data Register 1 (SR1L: $006, SR1U: $007): This register has the following functions (figures 72 and 73) * Serial interface 1 transmission data write and shift * Serial interface 1 receive data shift and read Writing data in this register is output from the SO1 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI1 pin at the rising edge of the transmit clock. Input/output timing is shown in figure 74. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed.
Serial data register 1 (lower digit) (SR1L: $006) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR13 R/W SR12 R/W SR11 R/W SR10
Figure 72 Serial Data Register 1 (SR1L)
90
HD404449 Series
Serial data register 1 (upper digit) (SR1U: $007) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR17 R/W SR16 R/W SR15 R/W SR14
Figure 73 Serial Data Register 1 (SR1U)
Transmit clock 1 Serial output data LSB 2 3 4 5 6 7 8 MSB
Serial input data latch timing
Figure 74 Serial Interface Output Timing
91
HD404449 Series
Port Mode Register A (PMRA: $004): This register has the following functions (figure 75). * * * * R4 2/SI 1 pin function selection R4 3/SO 1 pin function selection R5 2/SI 2 pin function selection R5 3/SO 2 pin function selection
Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset.
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 0 W PMRA3 2 0 W 1 0 W 0 0 W
PMRA2 PMRA1 PMRA0
PMRA0 0 1 PMRA1 0 1 PMRA2 0 1 PMRA3 0 1
R43/SO1 mode selection R43 SO1 R42/SI1 mode selection R42 SI1 R53/SO2 mode selection R53 SO2 R52/SI2 mode selection R52 SI2
Figure 75 Port Mode Register A (PMRA)
92
HD404449 Series
Miscellaneous Register (MIS: $00C): This register has the following functions (figure 76). * R4 3/SO 1 pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS1 0
MIS0 0
tRC 0.12207 ms 0.24414 ms*
1 1 0 1 MIS2 0 1 MIS3 0 1
7.8125 ms 62.5 ms Not used
R43/SO1 PMOS on/off selection On Off Pull-up MOS on/off selection Off On
Note: *This value is valid only for direct transfer operation.
Figure 76 Miscellaneous Register (MIS) Serial Mode Register 2A (SM2A: $01B): This register has the following functions (figure 77). * * * * R5 1/SCK 2 pin function selection Serial interface 2 transmit clock selection Serial interface 2 prescaler division ratio selection Serial interface 2 initialization
Serial mode register 2A (SM2A: $01B) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register 2A (SM2A: $01B) discontinues the input of the transmit clock to serial data register 2 (SR2L: $01D, SR1U: $01E) and the octal counter, and the octal counter is reset to
93
HD404449 Series
000. Therefore, if a write is performed during data transfer, the serial 2 interrupt request flag (IFS2: $023, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the SM2A read instruction must be executed at least two cycles after that.
Serial mode register 2A (SM2A: $01B) Bit Initial value Read/Write Bit name 3 0 W SM2A3 2 0 W SM2A2 1 0 W SM2A1 0 0 W SM2A0
SM2A3 0 1
R51/SCK2 mode selection R51 SCK2
SM2A2 0
SM2A1 0
SM2A0 0 1
SCK2 Output
Clock source Prescaler
Prescaler division ratio Refer to table 29
1
0 1
1
0
0 1
1
0 1
Output Input
System clock External clock
-- --
Figure 77 Serial Mode Register 2A (SM2A) Serial Mode Register 2B (SM2B: $01C): This register has the following functions (figure 78). * Serial interface 2 prescaler division ratio selection * Serial interface 2 output level control in idle states * R5 3/SO 2 pin PMOS control Serial mode register 2B (SM2B: $01C) is a 3-bit write-only register. It cannot be written during serial interface 2 data transfer. Bit 0 (SM2B0) and bit 2 (SM2B2) is reset to $0 by MCU reset. By setting bit 0 (SM2B0) of this register, the serial interface 2 prescaler division ratio of serial interface 2 is selected. By resetting bit 1 (SM2B1), the output level of the SO2 pin is controlled in idle states of serial interface 2. The output level changes at the same time that SM2B1 is written to.
94
HD404449 Series
Serial mode register 2B (SM2B: $01C) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W
1 Undefined W SM2B1
0 0 W SM2B0
Not used SM2B2
SM2B2 0 1
R53/SO2 PMOS On Off
SM2B0 0 1 SM2B1 0 1
Transmit clock division ratio Prescaler output divided by 2 Prescaler output divided by 4 Output level control in idle states Low level High level
Figure 78 Serial Mode Register 2B (SM2B) Serial Data Register 2 (SR2L: $01D, SR2U: $01E): This register has the following functions (figures 79 and 80). * Serial interface 2 transmission data write and shift * Serial interface 2 receive data shift and read Writing data in this register is output from the SO2 pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI2 pin at the rising edge of the transmit clock. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed.
Serial data register 2 (lower digit) (SR2L: $01D) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR23 R/W SR22 R/W SR21 R/W SR20
Figure 79 Serial Data Register 2 (SR2L)
95
HD404449 Series
Serial data register 2 (upper digit) (SR2U: $01E) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR27 R/W SR26 R/W SR25 R/W SR24
Figure 80 Serial Data Register 2 (SR2U)
96
HD404449 Series
A/D Converter
The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It can measure four analog inputs with 8-bit resolution. As shown in the block diagram of figure 81, the A/D converter has a 4-bit A/D mode register, a 1-bit A/D start flag, and a 4-bit plus 4-bit A/D data register.
Internal bus line (S2) 4 4 A/D mode register (AMR) 2 2 A/D start flag (ADSF)
Internal bus line (S1)
4
A/D data register (ADRU, ADRL) 8 IFAD
AN 0 AN 1 AN 2 AN 3
Selector
A/D interrupt request flag
+ COMP AVCC - Control logic Encoder
AVSS
D/A
8 Operating mode signal (set to 0 in stop mode, watch mode, and subactive mode)
Figure 81 A/D Converter Block Diagram A/D Mode Register (AMR: $016): Four-bit write-only register which selects the A/D conversion period and indicates analog input pin information. Bit 0 of the A/D mode register selects the A/D conversion period, and bits 2 and 3 select a channel, as shown in figure 82. A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is cleared. Refer to figure 86. A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 83, 84, and 85).
97
HD404449 Series
Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2), but make sure that the A/D start flag is not written to during A/D conversion. Data read from the A/D data register (ADRL: $017, ADRU: $018) during A/D conversion cannot be guaranteed. The A/D converter does not operate in the stop, watch, and subactive modes because of the OSC clock. During these low-power dissipation modes, current through the resistor ladder is cut off to decrease the power input.
A/D mode register (AMR: $016) Bit Initial value Read/Write Bit name 3 0 W AMR3 2 0 W 1 -- -- 0 0 W AMR0
AMR2 Not used
AMR3 0 0 1 1
AMR2 0 1 0 1
Analog input selection AN0 AN1 AN2 AN3
AMR0 0 1
Conversion time 34tcyc 67tcyc
Figure 82 A/D Mode Register (AMR)
ADRU: $018 3 2 1 0 3 ADRL: $017 2 1 0
MSB Bit 7
LSB Bit 0
Figure 83 A/D Data Registers
98
HD404449 Series
A/D data register (lower digit) (ADRL: $017) Bit Initial value Read/Write Bit name 3 0 R ADRL3 2 0 R ADRL2 1 0 R ADRL1 0 0 R ADRL0
Figure 84 A/D Data Register Lower Digit (ADRL)
A/D data register (upper digit) (ADRU: $018) Bit Initial value Read/Write Bit name 3 1 R ADRU3 2 0 R ADRU2 1 0 R 0 0 R
ADRU1 ADRU0
Figure 85 A/D Data Register Upper Digit (ADRU)
99
HD404449 Series
A/D start flag (ADSF: $020, bit 2) Bit Initial value Read/Write Bit name 3 0 R/W DTON 2 0 R/W ADSF 1 0 R/W WDON 0 0 R/W LSON
LSON Refer to the description of operating modes WDON Refer to the description of timers
ADSF (A/D start flag) 1 0 A/D conversion started A/D conversion completed DTON Refer to the description of operating modes
Figure 86 A/D Start Flag (ADSF)
100
HD404449 Series
Notes on Mounting
Assemble all parts including the HD404449 Series on a board, noting the points described below. 1. Connect layered ceramic type capacitors (about 0.1 F) between AVCC and AVSS , between VCC and GND, and between used analog pins and AVSS . 2. Connect unused analog pins to AVSS .
* When not using an A/D converter
VCC
AVCC AN 0 0.1 F AN 1 AN 2 AN 3 AVSS
GND
* When using pins AN0 and AN1 but not using AN2 and AN3 AVCC AN 0 AN 1 AN 2 AN 3 GND 0.1 F x 3 AVSS
VCC
* When using all analog pins AVCC AN 0 AN 1 AN 2 AN 3 AVSS 0.1 F x 5
VCC
GND
Figure 87 Example of Connections (1)
101
HD404449 Series
Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 88. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2.
VCC C1 C2
VCC
GND
GND
Figure 88 Example of Connections (2)
102
HD404449 Series
Programmable ROM (HD4074449)
The HD4074449 is a ZTATTM microcomputer with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description
MCU Mode Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AN 2 AN 3 AVSS TEST OSC 1 OSC 2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D13/INT0 R0 0/INT1 R0 1/INT2 R0 2/INT3 R0 3 R1 0 R1 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O A5 A6 I I A13 A14 A9 VPP M0 M1 I I I I I I I O I I O GND CE OE VCC VCC I I RESET GND I I/O I I GND TEST VCC I PROM Mode Pin Name I/O Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 MCU Mode Pin Name R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 R3 0/TOB R3 1/TOC R3 2/TOD R3 3/EVNB R4 0/EVND R4 1/SCK 1 R4 2/SI1 R4 3/SO 1 R5 0 R5 1/SCK 2 R5 2/SI2 R5 3/SO 2 R6 0 R6 1 R6 2 R6 3 R7 0 R7 1 R7 2 R7 3 R8 0 R8 1 R8 2 R8 3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A1 A2 A3 A4 O0 O1 O2 O3 O4 O5 O6 O7 I I I I I/O I/O I/O I/O I/O I/O I/O I/O PROM Mode Pin Name A7 A8 A0 A10 A11 A12 I/O I I I I I I
D12/STOPC I
103
HD404449 Series
MCU Mode Pin No. Pin Name 61 62 63 64 65 66 67 68 69 70 R9 0 R9 1 R9 2 R9 3 RA 0 RA 1 RA 2 RA 3 RB 0 RB 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PROM Mode Pin Name O4 O3 O2 O1 O0 VCC I/O I/O I/O I/O I/O I/O Pin No. 71 72 73 74 75 76 77 78 79 80 MCU Mode Pin Name RB 2 RB 3 RC0 RC1 RC2 RC3 VCC AVCC AN 0 AN 1 I I I/O I/O I/O I/O I/O I/O I/O VCC VCC PROM Mode Pin Name I/O
Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. Each of O0-O4 has two pins; before using, each pair must be connected together.
104
HD404449 Series
Programming the Built-In PROM The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 89. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and an 80-to-28-pin socket adapter. Recommended PROM programmers and socket adapters of the HD4074449 are listed in table 31. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000-$7FFF) must be specified. Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased or reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP): 12.5 V and 21 V. Remember that ZTATTM devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as listed in table 30. For details of PROM programming, refer to the following section, Notes on PROM Programming. Table 30 PROM Mode Selection
Pin Mode Programming Verification Programming inhibited CE Low High High OE High Low High VPP VPP VPP VPP O0-O7 Data input Data output High impedance
105
HD404449 Series
Table 31 Recommended PROM Programmers and Socket Adapters
Socket Adapter Model Name 121B 29B TFP-80F AVAL Corp. PKW-1000 Hitachi FP-80A TFP-80F HS4449ESN01H HS444ESH01H HS4449ESN01H Manufacturer Hitachi Package FP-80A Model Name HS444ESH01H
PROM Programmer Manufacturer DATA I/O Corp.
VCC VCC RESET TEST M0 M1 AVCC
VCC
VCC
VPP
O0 to O7 VPP VCC OSC1 D2 D3 RA1 X1 AVSS GND HD4074449 A0 to A14
Data O0 to O7
Address A0 to A14
OE CE
OE CE
Figure 89 PROM Mode Connections
106
HD404449 Series
Addressing Modes
RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 90 and described below.
W register W1 W0 X3 X register X2 X1 X0 Y3 Y register Y2 Y 1 Y0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Direct Addressing
1st word of Instruction Opcode d
9
2nd word of Instruction d8 d7 d6 d5 d4 d3 d2 d1 d0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction Opcode 0 0 0 1 0 0 m3 m2 m1 m0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 90 RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. When the area from $090 to $25F is used, a bank must be selected by the bank register (V: $03F). Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address.
107
HD404449 Series
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 91 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 93. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 92. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter.
108
HD404449 Series
[JMPL] [BRL] [CALL] 1st word of instruction Opcode p3 p2 p1 p0 d9 d8 2nd word of instruction d7 d6 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 0 Opcode 0 0 0 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction
[TBR]
Opcode
p3
p2
p1
p0 B register B3 B2 B1 B0 A3 Accumulator A2 A1 A0
0 Program counter
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 91 ROM Addressing Modes
109
HD404449 Series
Instruction [P] Opcode p3 p2 p1 p0 B3 0 0 B register B2 B1 B0 A3 Accumulator A2 A1 A0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10 Pattern Output
If RO 9 = 1
Figure 92 P Instruction
256 (n - 1) + 255 BR AAA 256n
AAA
NOP
BR BR
AAA BBB
256n + 254 256n + 255 256 (n + 1)
BBB
NOP
Figure 93 Branching when the Branch Destination is on a Page Boundary
110
HD404449 Series
Absolute Maximum Ratings
Item Supply voltage Programming voltage Pin voltage Total permissible input current Total permissible output current Maximum input current Symbol VCC VPP VT Io -Io Io Value -0.3 to +7.0 -0.3 to +14.0 Unit V V 1 Notes
-0.3 to (VCC + 0.3) V 100 50 4 30 mA mA mA mA mA C C 2 3 4, 5 4, 6 7, 8
Maximum output current Operating temperature Storage temperature
-I o Topr Tstg
4 -20 to +75 -55 to +125
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal opera-tion must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D 13 (VPP) of the HD4074449. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to D 10 , D11, and R0-RC. 6. Applies to D 0-D 9. 7. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 8. Applies to D 0-D 11 and R0-RC.
111
HD404449 Series
Electrical Characteristics
DC Characteristics (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074449: V CC = 2.7 to 5.5 V, GND = 0 V, T a = -20C to +75C, unless otherwise specified)
Item Input high voltage Symbol VIH Pin(s) RESET, STOPC, INT0, INT1, INT2, INT3, SCK 1, SI 1, SCK 2, SI 2, EVNB, EVND OSC 1 Input low voltage VIL RESET, STOPC, INT0, INT1, INT2, INT3, SCK 1, SI 1, SCK 2, SI 2, EVNB, EVND OSC 1 Output high VOH voltage SCK 1, SO1, SCK 2, SO2, TOB, TOC, TOD Output low VOL voltage SCK 1, SO1, SCK 2, SO2, TOB, TOC, TOD I/O leakage | IIL | current RESET, STOPC, INT0, INT1, INT2, INT3, SCK 1, SI 1, SCK 2, SI 2, SO1, SO2, EVNB, EVND, OSC 1, TOB, TOC, TOD I CC1 Current dissipation in active mode I CC2 VCC -- 5 9 mA VCC = 5.0 V, f OSC = 4 MHz 2 -- -- 1.0 A Vin = 0 V to VCC 1 -- -- 0.4 V I OL = 0.4 mA -0.3 VCC - 1.0 -- -- 0.3 -- V V External clock operation -I OH = 0.5 mA VCC - 0.3 -0.3 -- -- VCC + 0.3 0.1V CC V V External clock operation -- Min 0.9V CC Typ -- Max VCC + 0.3 Unit V Test Condition -- Notes
VCC
--
0.6
1.8
mA
VCC = 3.0 V, f OSC = 800 kHz
2
112
HD404449 Series
Item Current dissipation in standby mode Symbol I SBY1 I SBY2 Current dissipation in subactive mode I SUB Pin(s) VCC VCC VCC Min -- Typ 1.2 Max 3 Unit mA Test Condition VCC = 5.0 V, f OSC = 4 MHz -- 0.2 0.7 mA A A A A V VCC = 3.0 V, f OSC = 800 kHz -- 35 70 VCC = 3.0 V, 32-kHz oscillator -- 70 150 VCC = 3.0 V, 32-kHz oscillator Current dissipation in watch mode Current dissipation in stop mode I WTC I STOP VCC VCC VCC -- 8 15 VCC = 3.0 V, 32-kHz oscillator -- 1 10 VCC = 3.0 V, no 32-kHz oscillator 2 -- -- No 32-kHz oscillator 7 6 6 5 4 3 Notes 3
Stop mode retaining VSTOP voltage
Notes: 1. Output buffer current is excluded. 2. I CC1 and I CC2 are the source currents when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at V CC (VCC - 0.3 V to VCC) TEST at V CC (VCC - 0.3 V to VCC) 3. I SBY1 and I SBY2 are the source currents when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC - 0.3 V to VCC) 4. Applies to HD404448 and HD404449. 5. Applies to HD4074449. 6. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC - 0.3 V to VCC) D13 (VPP) at V CC (VCC - 0.3 V to VCC) for the HD4074449 7. RAM data retention.
113
HD404449 Series
I/O Characteristics for Standard Pins (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, T a = - 20C to +75C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Output low voltage I/O leakage current Symbol VIH VIL VOH VOL IIL Pin(s) D10-D 13 , R0-RC D10-D 13 , R0-RC D10, D11, R0-RC D10, D11, R0-RC D10-D 13 , R0-RC D10-D 12 , R0-RC D13 D13 Pull-up MOS -I PU current D10, D11, R0-RC -- -- 5 -- -- 30 1 20 90 A A A Vin = VCC - 0.3 V to VCC 1, 3 Vin = 0 V to 0.3 V VCC = 3.0 V, Vin = 0 V 1, 3 -- -- 1 A Vin = 0 V to VCC 1, 3 -- -- 1 A Vin = 0 V to VCC 1, 2 -- -- 0.4 V I OL = 0.4 mA VCC - 1.0 -- -- V -I OH = 0.5 mA -0.3 -- 0.3V CC V -- Min 0.7V CC Typ -- Max Unit Test Condition -- Notes
VCC + 0.3 V
Notes: 1. Output buffer current is excluded. 2. Applies to HD404448 and HD404449. 3. Applies to HD4074449.
114
HD404449 Series
I/O Characteristics for High-Current Pins (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Input high voltage Input low voltage Symbol VIH VIL Pin(s) D0-D 9 D0-D 9 D0-D 9 D0-D 9 Min 0.7V CC -0.3 Typ -- -- Max Unit Test Condition -- -- -I OH = 0.5 mA I OL = 0.4 mA I OL = 15 mA, VCC 4.5 V I/O leakage current IIL D0-D 9 D0-D 9 -- 5 -- 30 1 90 A A Vin = 0 V to VCC VCC = 3.0 V, Vin = 0 V Notes: 1. Output buffer current is excluded. 1 Notes
VCC + 0.3 V 0.3V CC -- 0.4 2.0 V V V V
Output high voltage VOH Output low voltage VOL
VCC - 1.0 -- -- -- -- --
Pull-up MOS current -I PU
A/D Converter Characteristics (HD404448, HD404449: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Analog power voltage Analog input voltage Current between AVCC and AVSS Analog input capacitance Resolution Number of inputs Symbol AVCC AVin I AD CA in -- -- Pin(s) AVCC Min Typ Max Unit Test Condition -- -- VCC = AVCC = 5.0 V -- Notes 1
VCC - 0.3 VCC -- 50 15 8 -- --
VCC + 0.3 V AVCC 150 -- 8 4 2.0 67 -- V A pF Bit Channel LSB
AN 0-AN 3 AVSS -- --
AN 0-AN 3 -- -- -- -- 8 0 --
-- Ta = 25C, VCC = 4.5 V to 5.5 V -- f OSC = 1 MHz, Vin = 0 V
Absolute accuracy --
Conversion time Input impedance Note:
-- --
--
34
-- --
t cyc M
AN 0-AN 3 1
1. AVCC 2.7 V
115
HD404449 Series
AC Characteristics (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Clock oscillation frequency Symbol f OSC Pin(s) OSC 1, OSC 2 X1, X2 Instruction cycle time t cyc t subcyc -- -- Min Typ 0.4 -- 1.0 -- Max Unit 4.0 32.768 -- -- 10 MHz kHz s s s ms Test Condition 1/4 division -- -- 32-kHz oscillator, 1/8 division -- 122.07 -- 32-kHz oscillator, 1/4 division Oscillation stabilization time (ceramic) Oscillation stabilization time (crystal) t RC OSC 1, OSC 2 -- -- 7.5 -- 2 1 Notes 1
244.14 --
t RC
OSC 1, OSC 2
--
--
40
ms
HD404448, HD404449 VCC=3.0 to 6.0V HD4074449 VCC=3.5 to 5.5V -- Ta = -10C to +60C -- -- -- -- --
2
-- X1, X2 External clock high t CPH width External clock low t CPL width External clock rise t CPr time External clock fall time t CPf OSC 1 OSC 1 OSC 1 OSC 1 INT0-INT3, EVNB, EVND INT0-INT3, EVNB, EVND RESET STOPC RESET STOPC 2 1 -- -- 2 --
-- --
60 3 -- -- 20 20 --
ms s ns ns ns ns t cyc / t subcyc t cyc / t subcyc t cyc t RC ms ms
2 3 4 4 4 4 5
105 -- 105 -- -- -- 2 -- -- --
INT0-INT3, EVNB, t IH EVND high widths INT0-INT3, EVNB, t IL EVND low widths RESET high width t RSTH STOPC low width RESET fall time STOPC rise time t STPL t RSTf t STPr
--
--
--
5
-- -- -- --
-- -- 20 20
-- -- -- --
6 7 6 7
116
HD404449 Series
Item Input capacitance Symbol Cin Pin(s) Min Typ -- -- Max 15 15 Unit pF pF Test Condition f = 1 MHz, Vin = 0 V HD404448, HD404449: f = 1 MHz, Vin = 0 V -- -- 180 pF HD4074449: f = 1 MHz, Vin = 0 V Notes: 1. If the 32.768-kHz oscillator is used for the subsystem oscillator, f OSC must be set as 0.4 MHz f OSC 1.0 MHz or 1.6 MHz fOSC 4.0 MHz, and bit 1 of the system clock selector register (SSR: $029) must be set to 0 or 1, respectively. 2. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC reaches 2.7 V at power-on, or after RESET input goes high or STOPC input goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. Set bits 0 and 1 (MIS0, MIS1) of the miscellaneous register (MIS: $00C) according to the system oscillation of the oscillation stabilization time. 3. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC reaches 2.7 V at power-on, or after RESET input goes high or STOPC input goes low when the 32-kHz oscillator stops in stop mode and stop mode is cancelled. If using a crystal oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. 4. Refer to figure 94. 5. Refer to figure 95. The t cyc unit applies when the MCU is in standby or active mode. The tsubcyc unit applies when the MCU is in watch or subactive mode. 6. Refer to figure 96. 7. Refer to figure 97. Notes All pins except D13 -- D13 --
117
HD404449 Series
Serial Interface Timing Characteristics (HD404448, HD404449: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = - 20C to +75C; HD4074449: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) During Transmit Clock Output
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Symbol Pin t Scyc t SCKH t SCKL Min Typ -- -- -- -- -- -- -- -- Max -- -- -- 200 200 500 -- -- Unit t cyc t Scyc t Scyc ns ns ns ns ns Test Condition Note
SCK 1, SCK 2 1.0 SCK 1, SCK 2 0.5 SCK 1, SCK 2 0.5 SCK 1, SCK 2 -- SCK 1, SCK 2 -- SO1, SO2 SI 1, SI 2 SI 1, SI 2 -- 300 300
Load shown in figure 99 1 Load shown in figure 99 1 Load shown in figure 99 1 Load shown in figure 99 1 Load shown in figure 99 1 Load shown in figure 99 1 -- -- 1 1
Transmit clock rise time t SCKr Transmit clock fall time t SCKf
Serial output data delay t DSO time Serial input data setup time Serial input data hold time Note: t SSI t HSI
1. Refer to figure 98.
During Transmit Clock Input
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Symbol Pin t Scyc t SCKH t SCKL Min Typ -- -- -- -- -- -- -- -- Max Unit -- -- -- 200 200 500 -- -- t cyc t Scyc t Scyc ns ns ns ns ns Test Condition -- -- -- -- -- Note 1 1 1 1 1
SCK 1, SCK 2 1.0 SCK 1, SCK 2 0.5 SCK 1, SCK 2 0.5 SCK 1, SCK 2 -- SCK 1, SCK 2 -- SO1, SO2 SI 1, SI 2 SI 1, SI 2 -- 300 300
Transmit clock rise time t SCKr Transmit clock fall time t SCKf
Serial output data delay t DSO time Serial input data setup time Serial input data hold time Note: t SSI t HSI
Load shown in figure 99 1 -- -- 1 1
1. Refer to figure 98.
118
HD404449 Series
OSC1 VCC - 0.3 V 0.3 V tCPH tCPr tCPf 1/fCP tCPL
Figure 94 External Clock Timing
INT0 to INT3, EVNB, EVND
0.9VCC 0.1VCC
tIH
tIL
Figure 95 Interrupt Timing
RESET
0.9VCC 0.1VCC tRSTH tRSTf
Figure 96 Reset Timing
STOPC
0.9VCC 0.1VCC
tSTPL tSTPr
Figure 97 STOPC Timing
119
HD404449 Series
t Scyc t SCKf SCK 1 VCC - 2.0 V (0.9VCC )* 0.4 V (0.1VCC)* SCK 2 t DSO SO1 SO2 VCC - 0.5 V 0.4 V t SSI SI1 SI2 0.9V CC 0.1VCC t HSI t SCKL t SCKH t SCKr
Note: * VCC - 2.0 V and 0.4 V are the threshold voltages for transmit clock output, and 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input.
Figure 98 Serial Interface Timing
VCC RL = 2.6 k Test point C= 30 pF R= 12 k 1S2074 H or equivalent
Figure 99 Timing Load Circuit
120
HD404449 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404449). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a16-kword version. This limitation applies when using an EPROM or a data base.
ROM 8-kword version: HD404448 Address $2000-$3FFF
$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (8,192 words) $1FFF $2000 Not used $3FFF
Fill this area with 1s
121
HD404449 Series
HD404448, HD404449 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order Customer 1. ROM size HD404448 HD404449 2. Optional Functions * * With 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 8-kword 16-kword Department Name ROM code name LSI number HD40444
4. Oscillator for OSC1 and OSC2 Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
5. Stop mode Used Not used
6. Package FP-80A TFP-80F
122
HD404449 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
123

▲Up To Search▲

Price & Availability of HD404448

	To Download HD404448 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .